The present invention relates to voltage generating circuits, and, more particularly, to a method and circuit for generating a pumped output voltage from a low input voltage.
In many electronic circuits, charge pump circuits are utilized to generate a positive pumped voltage having an amplitude greater than that of a positive supply voltage, or to generate a negative pumped voltage from the positive supply voltage, as understood by those skilled in the art. For example, a typical application of a charge pump circuit is in a conventional dynamic random access memory (xe2x80x9cDRAMxe2x80x9d), to generate a boosted word line voltage VCCP having an amplitude greater than the amplitude of a positive supply voltage VCC or a negative substrate or back-bias voltage Vbb that is applied to the bodies of NMOS transistors in the DRAM. A charge pump may also be utilized in the generation of a programming voltage VPP utilized to program data into memory cells in non-volatile electrically block-erasable or xe2x80x9cFLASHxe2x80x9d memories, as will be understood by those skilled in the art.
FIG. 1a is a block diagram of a dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) 100 including a charge pump circuit. The DRAM 100 includes an address decoder 102, control circuit 104, and read/write circuitry 106, all of which are conventional. The address decoder 102, control circuit 104, and read/write circuitry 106 are all coupled to a memory-cell array 108. In addition, the address decoder 102 is coupled to an address bus, the control circuit 104 is coupled to a control bus, and the read/write circuit 106 is coupled to a data bus. The pumped output voltage VCCP from a charge pump circuit 110 may be applied to a number of components within the DRAM 100, as understood by those skilled in the art. In the DRAM 100, the charge pump circuit 110 applies the pumped output voltage VCCP to the read/write circuitry 106, which may utilize this voltage in a data buffer (not shown) to enable that buffer to transmit or receive full logic level signals on the data bus. The charge pump circuit 110 also applies the voltage VCCP to the address decoder 102 which, in turn, may utilize the voltage to apply boosted word line voltages to the array 108. In operation, external circuitry, such as a processor or memory controller, applies address, data, and control signals on the respective busses to transfer data to and from the DRAM 100.
FIG. 1b is a functional block diagram of an electrically erasable and programmable or FLASH memory 150 having an array 152 of FLASH cells (not shown), and including a charge pump 153. When contained in a FLASH memory, the charge pump circuit 153 would typically generate a boosted programming voltage VPP that is utilized to program data into nonvolatile memory cells in the array 152, as understood by those skilled in the art. The FLASH memory 150 includes an address decoder 154, control circuit 156, and read/program/erase circuitry 158 receiving signals on address, control, and data busses, respectively. The address decoder 154, control circuit 156, and circuitry 158 are conventional components, as understood by those skilled in the art. During programming, the control circuit 156 and read/program/erase circuitry 158 utilize the boosted voltage VPP generated by the charge pump circuit 153 to provide the memory-cell array 152 with the required high voltage for programming FLASH memory cells in the array; as understood by those skilled in the art. The address decoder 154 decodes address signals applied on the address bus and utilizes the boosted voltage VPP to access corresponding FLASH memory cells or blocks of memory cells in the array 152. The circuit 158 places read data from addressed cells in the array 152 onto the data bus during normal operation of the FLASH memory 150.
FIG. 2a illustrates a conventional charge pump circuit 200. A pulse generator 204, typically driven by a clock signal CLK, provides pulse signals to a boot circuit 208 which generates a pumped voltage VCCP. The boot circuit 208 includes two ump stages 210 and 212 that operate in an interleaved fashion to provide a VCCP voltage at an output node 250. The pump stages 210 and 212 are identical, and the following description of the pump stage 210 can be applied to the pump stage 212. FIG. 2b shows a signal diagram illustrating the signals at a boot node 220 and a node 230. Prior to time t0, the nodes 220 and 230 are pre-charged to VCC through transistors 270 and 272, respectively. The gates of the transistors 270 and 272 are coupled to nodes 232 and 222, respectively, to allow for the full VCC voltage to be applied to the respective nodes during pre-charge. Similarly, nodes 222 and 232 are pre-charged to VCC through transistors 274 and 276, which have gates coupled to the nodes 230 and 220, all respectively.
At time t0, the pulse generator 204 provides a HIGH output signal to the pump stage 210. In response, the boot node 220 is booted through a capacitor 264. Similarly, as seen in FIG. 2b, a capacitor 260 boots the node 230 as well. However, note that the voltage at the node 230 is not sufficient to switch transistor 244 ON. Eventually, at a time t1, the pulse generator provides a HIGH output signal to the capacitor 262 to further drive the node 230. At this time, the voltage on the node 230 is booted to a level sufficient to switch ON the transistor 244 in order to charge the output node 250. From time t1 to t2, the boot node 220 discharges into the output node 250. At a time t2, in response to the signal applied to the capacitors 262 and 264 going LOW, the voltage of the nodes 220 and 230 go LOW as well. Although not shown in FIG. 2b, the voltage of the nodes 222 and 232 of the pump stage 212 behave in a manner similar to that shown for the pump stage 210 during the time the pump stage 210 is inactive, that is, between times t2 and t3. As a result, the output voltage VCCP can be maintained at a relatively constant elevated voltage level.
Although the conventional charge pump circuit 200 can provide a pumped voltage VCCP, the efficiency of the charge pump circuit 200 may become an issue as device operating voltages continue to decrease. In a sever case where the operating voltage is too low, the output of such a charge pump circuit may not be sufficient to drive the circuitry requiring pumped voltages. A simple solution has been to include multiple boot circuits to provide sufficient drive levels. However, this solution typically results in increased power consumption, and increased pump size, and consequently, increased die size, which are generally considered undesirable. Therefore, there is a need for a charge pump circuit that can efficiently generate a sufficient pumped output voltage from relatively a low supply voltage.
The present invention is directed to an apparatus and method for generating an elevated output voltage in response a first set of pulses during a first phase and a second set of pulses during a second phase. The apparatus includes first and second boot nodes at which a respective elevated voltage is generated, first and second gate nodes, and an output node at which the elevated output voltage is provided. The apparatus further includes first and second switches, each having a gate terminal coupled to a respective gate node. The first switch couples the first boot node to the output node during a first portion of the first phase and the second switch couples the second boot node to the output node during a first portion of the second phase. A third switch couples to the first and second boot nodes for providing a conductive path through which charge can be shared between the first and second boot nodes during a second portion of the first and second phases.